The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Dec. 08, 1999
Qing Zhu, Castro Valley, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for allocating decoupling capacitance in a power grid is provided. A power grid model of an RLC network is evaluated to identify the power nodes that have peak voltages exceeding a minimum voltage threshold and a maximum voltage threshold. For each noisy node that violates the thresholds, a decoupling capacitor is inserted. The power grid is once again re-evaluated to determine of any of the power nodes still violate the voltage thresholds. For those violating power nodes, the size of the decoupling capacitor is incremented. This process of incrementing the size of the decoupling capacitance and re-evaluating the power grid is repeated until all the power nodes are within a noise budget or the noise level for each power node is within the thresholds. The decoupling capacitance is then re-evaluated as it is iteratively decremented while maintaining the power noise within the thresholds. This method of inserting and sizing decoupling capacitance allows the power noise thresholds, to be satisfied while optimizing the size of the decoupling capacitance.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile