Taipei, Taiwan

Ping-Chung Liu

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2016.


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2016

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1 patent (USPTO):Explore Patents

Title: Innovations of Ping-Chung Liu in Semiconductor Technology

Introduction

Ping-Chung Liu is a notable inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology. His innovative work has led to the development of a unique semiconductor structure that enhances performance and efficiency.

Latest Patents

One of Ping-Chung Liu's key patents is titled "Semiconductor structure and manufacturing method thereof." This patent describes a semiconductor structure that includes a semiconductor substrate, a gate stack on the substrate, and a stress memorization technology (SMT) sidewall spacer. The gate stack consists of a gate dielectric layer and a gate electrode, while the SMT sidewall spacer provides stress for the channel region beneath the gate stack. This invention is crucial for improving the performance of semiconductor devices.

Career Highlights

Ping-Chung Liu is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His work at this prestigious company has allowed him to be at the forefront of semiconductor innovations. Liu's expertise and dedication have made him a valuable asset to his team.

Collaborations

Some of his notable coworkers include Wei-Chiang Hung and Hsiang-Yu Tsai. Their collaboration has contributed to advancements in semiconductor technology and has fostered a productive work environment.

Conclusion

Ping-Chung Liu's contributions to semiconductor technology through his innovative patents and work at Taiwan Semiconductor Manufacturing Company Limited highlight his importance in the field. His inventions continue to influence the development of advanced semiconductor structures.

Profile summary based on public USPTO records.
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