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For the Inventor, By the Inventor

Colchester, VT, United States of America

Phillip Francis Chapman

This inventor holds 18 USPTO granted patents and 1 published patent application. Top assignee: International Business Machines Corporation. Active years: 2001-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Phillip Francis Chapman. Retrieved from https://idiyas.com/inventor/phillip-francis-chapman

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 18 

% Patents Active = 61.1

Average Co-Inventor Count = 3.4

ph-index = 4

Forward Citations = 56(Granted Patents)


Location History:

  • Essex Junction, VT (US) (2011 - 2012)
  • Colchester, VT (US) (2001 - 2021)

Company Filing History:

goldMedal18 out of 166,351 
 
International Business Machines Corporation
 patents

Years Active: 2001-2021

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18 patents (USPTO):Explore Patents
1. 10978452 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2021-04-13),
2. 10170476 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2019-01-01),
3. 9842838 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2017-12-12),
4. 9397010 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2016-07-19),
5. 9275997 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2016-03-01),
6. 8987067 - Segmented guard ring structures with electrically insulated gap structures and design structures thereof (2015-03-24),
7. 8853789 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2014-10-07),
8. 8420518 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2013-04-16),
9. 8212332 - Bias-controlled deep trench substrate noise isolation integrated circuit device structures (2012-07-03),
10. 8021941 - Bias-controlled deep trench substrate noise isolation integrated circuit device structures (2011-09-20),
11. 8017471 - Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry (2011-09-13),
12. 7855420 - Structure for a latchup robust array I/O using through wafer via (2010-12-21),
13. 7741681 - Latchup robust array I/O using through wafer via (2010-06-22),
14. 7696541 - Structure for a latchup robust gate array using through wafer via (2010-04-13),
15. 7549135 - Design methodology of guard ring design resistance optimization for latchup prevention (2009-06-16),

Title: The Innovations of Phillip Francis Chapman: A Pioneer in Semiconductor Technology

Introduction

Phillip Francis Chapman, an accomplished inventor based in Colchester, VT, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 18 patents, Chapman has exhibited remarkable ingenuity and dedication to advancing innovative solutions within the industry.

Latest Patents

Among his latest patents is a groundbreaking invention titled "Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry." This method pertains to manufacturing a semiconductor structure and includes several intricate steps: forming a trench in the back side of a substrate, depositing a dopant on the surfaces of the trench, and forming a shallow trench isolation (STI) structure on the top side of the substrate, among others. The innovation aims to enhance the robustness and reliability of semiconductor devices.

Career Highlights

Phillip Chapman currently works for the prestigious International Business Machines Corporation (IBM), a company renowned for its cutting-edge technology and innovation. His career is marked by a strong focus on semiconductor devices, specifically addressing the challenges associated with latchup in CMOS circuitry.

Collaborations

Throughout his career, Chapman has had the privilege of collaborating with talented colleagues, including David S. Collins and Steven H. Voldman. These partnerships have undoubtedly enriched his research and development efforts, leading to significant advancements in semiconductor technology.

Conclusion

Phillip Francis Chapman’s contributions as an inventor have paved the way for improved semiconductor structures and methodologies. With his extensive patent portfolio and collaborations, he continues to play a crucial role in the ongoing evolution of the technology landscape. His work not only enhances device performance but also exemplifies the spirit of innovation that drives the field forward.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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