The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7696541 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 13, 2010

Filed:

Mar. 06, 2008
Applicants:

Phillip Francis Chapman, Colchester, VT (US);

David S. Collins, Williston, VT (US);

Steven H. Voldman, South Burlington, VT (US);

Inventors:

Phillip Francis Chapman, Colchester, VT (US);

David S. Collins, Williston, VT (US);

Steven H. Voldman, South Burlington, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/112 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.


Find Patent Forward Citations

Chapman, Phillip. (2010). Structure for a latchup robust gate array using through wafer via (U.S. Patent No. 7696541). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7696541

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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