The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Jan. 12, 2016
Structure and method of latchup robustness with placement of through wafer via within cmos circuitry
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Phillip F. Chapman, Colchester, VT (US);
David S. Collins, Williston, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/74 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/743 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 27/092 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.