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San Jose, CA, United States of America

Philip A Bourekas

This inventor holds 13 USPTO granted patents. Top assignees: Integrated Device Technology, Inc., Other. Active years: 1992-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Philip A Bourekas. Retrieved from https://idiyas.com/inventor/philip-a-bourekas

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 8

Forward Citations = 308(Granted Patents)

Location History:

Sunnyvale, CA (US) (1992)
San Jose, CA (US) (1994 - 2006)

Company Filing History:

12 out of 1,264

Integrated Device Technology, Inc.

1 out of 834,453

Other

patents

Years Active: 1992-2006

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13 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7133951 - Alternate set of registers to service critical interrupts and operating system traps (2006-11-07),

2. 6598050 - Apparatus and method for limited data sharing in a multi-tasking system (2003-07-22),

3. 6128703 - Method and apparatus for memory prefetch operation of volatile (2000-10-03),

4. 5894176 - Flexible reset scheme supporting normal system operation, test and (1999-04-13),

5. 5694567 - Direct-mapped cache with cache locking allowing expanded contiguous (1997-12-02),

6. 5649232 - Structure and method for multiple-level read buffer supporting optimal (1997-07-15),

7. 5636363 - Hardware control structure and method for off-chip monitoring entries of (1997-06-03),

8. 5553268 - Memory operations priority scheme for microprocessors (1996-09-03),

9. 5517659 - Multiplexed status and diagnostic pins in a microprocessor with on-chip (1996-05-14),

10. 5386579 - Minimum pin-count multiplexed address/data bus with byte enable and (1995-01-31),

11. 5343435 - Use of a data register to effectively increase the efficiency of an (1994-08-30),

12. 5317711 - Structure and method for monitoring an internal cache (1994-05-31),

13. 5175859 - Apparatus for disabling unused cache tag input/output pins during (1992-12-29),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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