The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 1997

Filed:

Jun. 14, 1991
Applicant:
Inventors:

Philip A Bourekas, San Jose, CA (US);

Yeshayahu Mor, Cupertino, CA (US);

Scott Revak, Castro Valley, CA (US);

Assignee:

Integrated Device Technology, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395465 ;
Abstract

A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.


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Bourekas, Philip. (1997). Hardware control structure and method for off-chip monitoring entries of (U.S. Patent No. 5636363). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5636363

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