The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 1999
Filed:
May. 04, 1994
Philip A Bourekas, San Jose, CA (US);
Avigdor Willenz, Campbell, CA (US);
Yeshayahu Mor, Cupertino, CA (US);
Integrated Device Technology, Inc., Santa Clara, CA (US);
Abstract
A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.