Integrated Device Technology, Inc.

Other

Philip A Bourekas

Yeshayahu Mor

Avigdor Willenz

Scott Revak

Michael J Miller

Danh Le Ngoc

Yehayahu Mor

Andrew P Ng

Tuan Anh Luong

Danh LeNgoc

A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted 'fast' exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i.e., critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception. Advantageously, during the servicing of the exception, the values of the exception registers may be modified, without disrupting the state of the interrupted task. Thus, because a set of dedicated exception registers are swapped in for the general purpose registers to service an exception, there is no need for explicit state management prior to or after servicing the exception.

Alternate set of registers to service critical interrupts and operating system traps

An enhanced translation lookaside buffer (TLB), which translates a virtual address into a physical address, permits sharing of data or programs among a subset of all tasks through the use of a group membership field. Each entry in the TLB includes a global bit indicating that all tasks should have access to the translation, an address space identifier identifying an individual task that should have access to the translation and a group membership field identifying a group of tasks that have access to the entry, wherein the group of tasks is a subset of all tasks. The virtual address also has a group membership field that is compared with a group membership field in the TLB entry. If the two group membership fields match, the current task is permitted to use the translation. Thus, a given translation within the TLB may be valid for all tasks, only an individual task, or a group of tasks.

Apparatus and method for limited data sharing in a multi-tasking system

An apparatus and method for prefetching data into a cache memory system is provided. A prefetch instruction includes a hint type that allows a programmer to designate whether, during a data retrieval operation, a hit in the cache is to be ignored or accepted. If accepted, the prefetch operation completes. If ignored, the prefetch operation retrieves data from the main memory, even though the cache believes it contains valid data at the requested memory location. Use of this invention in a multiple bus master processing environment provides the advantages of using a cache memory, i.e., burst reads and a relatively large storage space as compared to a register file, without incurring disadvantages associated with maintaining data coherency between the cache and main memory systems.

Method and apparatus for memory prefetch operation of volatile

A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.

Flexible reset scheme supporting normal system operation, test and

A direct mapped cache with cache locking according to one embodiment of the present invention includes a physical address latch and a multiplexing means. The multiplexing means receives the physical address from the physical address latch and exchanges a physical address tag bit with a physical address index bit to generate a cache tag address and a cache index address to divide the cache into two halves, each half servicing a contiguous address range of main memory.

Direct-mapped cache with cache locking allowing expanded contiguous

A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable RdCEn and acknowledge (Ack) signals. The RdCEn signal is provided as each memory word is available from the main memory. The Ack signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.

Structure and method for multiple-level read buffer supporting optimal

A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.

Hardware control structure and method for off-chip monitoring entries of

A structure and a method are provided to implement a memory bus arbiter, in which separate priorities are provided to instruction and data reads from the main memory. In one embodiment in a microprocessor with an on-chip cache, the present invention provides an arbiter which yields the memory bus, in decreasing priority order, to an ongoing bus transaction, a 'direct memory access' (DMA) request, an instruction read resulting from a cache miss, a pending write request, and a read request, including reference to an uncacheable portion of memory and a data cache miss.

Memory operations priority scheme for microprocessors

In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.

Multiplexed status and diagnostic pins in a microprocessor with on-chip

A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being accessed, and two independent address lines which can function as a counter to support the burst refill. Both block reads or single datum transfers are handled similarly: a single addressing phase with multiple data phases; and all addresses in the memory system; are derived directly from the same pins regardless of whether it is a block read or not. The system allows for low cost packaging while maintaining a variety of system capabilities.

Minimum pin-count multiplexed address/data bus with byte enable and

Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles, allowing the write buffer FIFO to make the space consumed by the current write available at the start, rather than at the end of the write cycle. This effectively makes the write buffer 'four and one-half' entries deep, thereby increasing performance of the buffer without adding additional FIFO entries.

Use of a data register to effectively increase the efficiency of an

A structure and a method are provided to bring internal signals of an integrated circuit to the external pins for monitoring purpose. In one embodiment, the signals on an internal bus between an on-chip cache and a CPU in a microprocessor are provided on the microprocessor's pins for a bidirectional data/address bus, when the bidirectional data/address bus is not used for data/address bus transactions with the main memory or the peripheral input/output devices. In this embodiment, reserved pins are used to selectively enable the address/data bus for bringing out the signals of the on-chip bus.

Structure and method for monitoring an internal cache

A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled.

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San Jose, CA, United States of America

Philip A Bourekas