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Kokubunji, Japan

Peter M Lee

USPTO Granted Patents = 7

Average Co-Inventor Count = 3.0

ph-index = 3

Forward Citations = 28(Granted Patents)

Location History:

Kokubunji, JP (1998)
Musashino, JP (2003 - 2006)
Tokyo, JP (2010 - 2012)

Company Filing History:

Renesas Technology Corp.

2 out of 42,508

Elpida Memory, Inc.

Years Active: 1998-2012

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7 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8285524 - Simulation method for transistor unsuitable for existing model (2012-10-09),

2. 7721234 - Simulation method and simulation program (2010-05-18),

3. 7123049 - Output buffer circuit with control circuit for modifying supply voltage and transistor size (2006-10-17),

4. 6952112 - Output buffer circuit with control circuit for modifying supply voltage and transistor size (2005-10-04),

5. 6937059 - Output buffer circuit with control circuit for modifying supply voltage and transistor size (2005-08-30),

6. 6634015 - Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit device (2003-10-14),

7. 5742071 - Wiringless logical operation circuits (1998-04-21),

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