Renesas Technology Corp.

Hitachi, Ltd.

Elpida Memory, Inc.

Peter M Lee

Shigezumi Matsui

Takashi Satou

Gouichi Yokomizo

Goichi Yokomizo

Junji Sato

Sigeo Ihara

Hitoshi Matsuo

Shiroo Kamohara

Yasuhiro Namba

A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.

Simulation method for transistor unsuitable for existing model

There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Simulation method and simulation program

In this invention, a control circuit () controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.

Output buffer circuit with control circuit for modifying supply voltage and transistor size

The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation&equals;Act ) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.

Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit device

A logical operation circuit in which wiring as generally performed between transistors is made unnecessary to improve reliability, stability and integration degree of a logical circuit using a tunnel phenomenon, for example, a single-electron tunnel phenomenon, or a flight phenomenon of a particle group. Conducting materials are arranged in a two-dimensional plane or three-dimensional space in the logical circuit. When two conducting materials are arranged to be nearest each other, the two conducting materials are connected, for example, by a single-electron tunnel phenomenon. When two conducting materials are arranged to be not nearest, there is no connection between the conducting materials by the tunnel phenomenon. Propagation of electrons is controlled by changing the arrangement. Further, because particles which have entered input regions move toward different flight directions respectively from a branch region on the basis of the property that two particles cannot enter simultaneously within an effective scatter distance by repulsive interaction between particles, flight of particles is controlled so as to enter or not branched particles into an observation region to thereby construct a wiringless logical operation circuit.

Growing community of inventors

Kokubunji, Japan

Peter M Lee