This inventor holds 5 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1996-1999.
Location History:
- Kanagawa-ken, JP (1996)
- Kawasaki, JP (1996 - 1997)
- Sheffield, GB (1998 - 1999)
Company Filing History:
Years Active: 1996-1999
Title: Innovations of Peter James Parbrook
Introduction
Peter James Parbrook is a notable inventor based in Kawasaki, Japan. He has made significant contributions to the field of semiconductor technology. With a total of 5 patents to his name, Parbrook has demonstrated a commitment to advancing innovation in his industry.
Latest Patents
Among his latest patents is a "Light emitter with lowered heterojunction interface barrier." This semiconductor device features a first semiconductor layer made of a specific semiconductor, a second semiconductor layer formed on the first, and a third semiconductor layer positioned between them. The third layer can either be a layer of a third semiconductor with a higher impurity concentration than the first layer or a layer of a fourth semiconductor with a higher impurity concentration than the second layer. Another significant patent is the "Semiconductor device having a hetero interface with a lowered barrier," which shares similar structural characteristics and innovations aimed at improving semiconductor performance.
Career Highlights
Peter James Parbrook is currently employed at Kabushiki Kaisha Toshiba, where he continues to work on groundbreaking semiconductor technologies. His expertise and innovative approach have positioned him as a key player in the field.
Collaborations
Parbrook has collaborated with notable colleagues such as Shinji Saito and Masaaki Onomura, contributing to various projects that enhance semiconductor technology.
Conclusion
Peter James Parbrook's work in semiconductor innovation exemplifies the impact of dedicated inventors in advancing technology. His patents reflect a deep understanding of semiconductor materials and their applications.