IDiyas

For the Inventor, By the Inventor

Jericho, VT, United States of America

Peter James Osler

USPTO Granted Patents = 8

Average Co-Inventor Count = 2.5

ph-index = 7

Forward Citations = 103(Granted Patents)


Company Filing History:

goldMedal8 out of 164,108 
 
International Business Machines Corporation
 patents

Years Active: 1992-2013

Loading Chart...
8 patents (USPTO):
1. 8495547 - Providing secondary power pins in integrated circuit design (2013-07-23),
2. 6829755 - Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis (2004-12-07),
3. 6795951 - Method and system for fault-tolerant static timing analysis (2004-09-21),
4. 6588000 - Method of partitioning large transistor design to facilitate transistor level timing (2003-07-01),
5. 6425110 - Incremental design tuning and decision mediator (2002-07-23),
6. 6023567 - Method and apparatus for verifying timing rules for an integrated (2000-02-08),
7. 5877965 - Parallel hierarchical timing correction (1999-03-02),
8. 5099415 - Guess mechanism for virtual address translation (1992-03-24),

Title: The Innovative Mind of Peter James Osler

Introduction

Peter James Osler is a prominent inventor based in Jericho, Vermont. With an impressive portfolio of 8 patents, he has made significant contributions to the field of integrated circuit design. His work primarily focuses on improving the efficiency and performance of application-specific integrated circuits (ASICs).

Latest Patents

Among Osler's latest innovations, two noteworthy patents stand out. The first is his patent for "Providing secondary power pins in integrated circuit design," which introduces an integrated circuit design featuring multiple metal layers. This design includes cells that require secondary power supply, where specific cells are equipped with secondary power stripes in a primary metal layer. These stripes strategically overlap with the primary power grid in a different metal layer, facilitating more efficient power routing through the IC design.

The second patent, titled "Variable detail automatic invocation of transistor level timing for application-specific integrated circuit static timing analysis," showcases a novel method for static timing analysis of ASICs. This method utilizes transistor level timing techniques that become active only when open channel circuit inputs are detected during the timing graph generation process, streamlining the analysis process and enhancing design accuracy.

Career Highlights

Peter Osler's career is closely tied to his work at International Business Machines Corporation (IBM), a leading technology company where he continues to innovate and impact the electronics industry. His contributions to IC design reflect a deep understanding of engineering principles, combined with practical applications in the tech sector.

Collaborations

Throughout his career, Osler has collaborated with talented individuals, including his coworkers David James Hathaway and Paul T. Gutwin. These partnerships have allowed for the exchange of ideas and expertise, further enriching the technological advancements they pursue together.

Conclusion

Peter James Osler's inventive spirit and dedication to improving integrated circuit designs have positioned him as a valuable contributor to the field. With his innovative patents and collaborations at IBM, he continues to push the boundaries of technology, setting the stage for future advancements in the world of electronics and beyond.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…