The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 1999

Filed:

Jun. 24, 1996
Applicant:
Inventors:

Nathaniel Douglas Hieter, Pleasant Valley, NY (US);

Charles Kenneth Hines, Poughkeepsie, NY (US);

Todd Edwin Leonard, Williston, VT (US);

Peter James Osler, Jericho, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
364490 ; 364488 ;
Abstract

A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.


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