International Business Machines Corporation

Peter James Osler

David James Hathaway

Paul T Gutwin

Joachim Keinert

Tad Jeffrey Wilder

Todd Edwin Leonard

Anthony DeGroff Drumm

Nathaniel Douglas Hieter

Charles B Winn

Douglass T Lamb

Fred T Tong

Charles Kenneth Hines

An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated.

Providing secondary power pins in integrated circuit design

A method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.

Variable detail automatic invocation of transistor level timing for application specific integrated circuit static timing analysis

A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K&plus;1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.

Method and system for fault-tolerant static timing analysis

A method and system for partitioning a large transistor design including transistors and transistor networks, and of the type having a top hierarchical design level and a second, lower hierarchical design level. The method comprises the steps of identifying a desired number of blocks for the second hierarchical level, representing the second hierarchical level as the desired number of blocks, each of the blocks having a boundary, and identifying transistor networks that extend across block boundaries. The method further comprises the steps of assigning transistor networks that cross block boundaries into the top hierarchical level to reduce cross boundary transistor networks, and re-assigning some of the transistors among the blocks to reduce the maximum number of transistors in any one block. Preferably, the transistors are assigned from one block to another by identifying partitions for groups of transistors; and then reassigning assigning transistors on the basis of said partitions. For example, the transistors may be partitioned on the basis of functionality, by name, to minimize connectivity, or to duplicate pre-existing hierarchy.

Method of partitioning large transistor design to facilitate transistor level timing

A method for analyzing and optimizing a design, such as a circuit design, which relates to the application of at least one optimization procedure, evaluating the benefit and net cost of the optimization procedure and then through the checkpoint manager, recording and reversing changes of the design. The execution and reversal of multiple optimizations may occur in a trial mode followed by evaluation of the executed and reversed designs and then the reinstatement of the best optimization.

Incremental design tuning and decision mediator

An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.

Method and apparatus for verifying timing rules for an integrated

A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.

Parallel hierarchical timing correction

A system providing a guess mechanism for improving the speed of translating effective addresses produced by a processor to real addresses in memory is disclosed wherein a set of Lookaside Tables and logic elements are used along with a set of validity registers and an MRU register to guess at the appropriate real frame index from one of the Tables to be output in the real address in the first cycle of a two cycle operation. The low order bits of the effective address are sent to index the Tables during the first cycle and the high order bits are used during the second cycle for comparison with the set of Table entries selected in the first cycle as containing the real frame index that is output. The selection of the actual real frame index that is output involves a guess using the validity and MRU registers along with indexing of the Tables by a portion of the low order bits. If the logic indicates, upon comparison of 1) the Table entry containing the real frame index that is output during the first cycle with 2) the high order bit comparison of the second cycle, that the selected real frame index was inappropriate, a signal is sent after the second cycle to invalidate the output of the real address incorporating that real frame index.

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Jericho, VT, United States of America

Peter James Osler