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For the Inventor, By the Inventor

Folsom, CA, United States of America

Peter J Smith

This inventor holds 9 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2006-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter J Smith. Retrieved from https://idiyas.com/inventor/peter-j-smith-o43k9939

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9

% Patents Active = 22.2

Average Co-Inventor Count = 2.9

ph-index = 3

Forward Citations = 49(Granted Patents)


Company Filing History:

goldMedal9 out of 56,290 
 
Intel Corporation
 patents

Years Active: 2006-2016

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9 patents (USPTO):Explore Patents
1. 9343126 - Frequency selection granularity for integrated circuits (2016-05-17),
2. 9229874 - Apparatus and method for compressing a memory address (2016-01-05),
3. 8775990 - Alignment of microarchitectural conditions (2014-07-08),
4. 7925834 - Tracking temporal use associated with cache evictions (2011-04-12),
5. 7689772 - Power-performance modulation in caches using a smart least recently used scheme (2010-03-30),
6. 7457917 - Reducing power consumption in a sequential cache (2008-11-25),
7. 7155574 - Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory (2006-12-26),
8. 7136992 - Method and apparatus for a stew-based loop predictor (2006-11-14),
9. 7124277 - Method and apparatus for a trace cache trace-end predictor (2006-10-17),
Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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