The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Dec. 28, 2012
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Harikrishna B. Baliga, Folsom, CA (US);
Peter J. Smith, Folsom, CA (US);
Joydeep Ray, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G11C 8/18 (2006.01); H03L 7/18 (2006.01); H03L 7/07 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); H03L 7/07 (2013.01); H03L 7/18 (2013.01);
Abstract
Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.