Paul F Findeis

This inventor holds 10 USPTO granted patents. Top assignees: International Business Machines Corporation, General Wire & Stamping Company, Incorporated, Globalfoundries Inc.. Active years: 1999-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Paul F Findeis. Retrieved from https://idiyas.com/inventor/paul-f-findeis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 80.0

Average Co-Inventor Count = 4.8

ph-index = 5

Forward Citations = 89(Granted Patents)

Location History:

Glenham, NY (US) (1999 - 2002)
Verbank, NY (US) (2012 - 2015)

Company Filing History:

9 out of 166,351

International Business Machines Corporation

patents

1 out of 1

General Wire & Stamping Company, Incorporated

where one patent can have more than one assignee

Years Active: 1999-2015

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10 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9177822 - Selective etching bath methods (2015-11-03),

2. 8394715 - Method of fabricating coaxial through-silicon via (2013-03-12),

3. 8298435 - Selective etching bath methods (2012-10-30),

4. 8242604 - Coaxial through-silicon via (2012-08-14),

5. 6448169 - Apparatus and method for use in manufacturing semiconductor devices (2002-09-10),

6. 6203690 - Process of reworking pin grid array chip carriers (2001-03-20),

7. 6149048 - Apparatus and method for use in manufacturing semiconductor devices (2000-11-21),

8. 6099935 - Apparatus for providing solder interconnections to semiconductor and (2000-08-08),

9. 6051119 - Plating structure for a pin grid array package (2000-04-18),

10. 5869139 - Apparatus and method for plating pin grid array packaging modules (1999-02-09),

Title: The Innovative Contributions of Paul F. Findeis

Introduction

Paul F. Findeis is a notable inventor based in Verbank, NY (US). He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work primarily focuses on etching methods and through-silicon via structures, which are essential in modern electronics.

Latest Patents

Among his latest patents is a method for selective etching bath methods. This etching method involves processing silicon wafers with specific etchants to achieve desired results. The process includes dissolving silicon dioxide (SiO) and silicon nitride (SiN) in a first etchant, leading to the precipitation of insoluble SiO. The method also details the combination of etchants to optimize etching rates for different materials. Another significant patent is for a method of fabricating coaxial through-silicon vias (TSVs). This innovative approach allows for the creation of unique interconnects within silicon substrates, enhancing the functionality and reliability of electronic devices.

Career Highlights

Throughout his career, Paul F. Findeis has worked with prominent companies such as IBM and General Wire & Stamping Company. His experience in these organizations has contributed to his expertise in semiconductor manufacturing and innovation.

Collaborations

Paul has collaborated with notable professionals in the field, including William Harrington Brearley and Laertis Economikos. These partnerships have fostered advancements in technology and have led to the development of groundbreaking inventions.

Conclusion

Paul F. Findeis is a distinguished inventor whose work has significantly impacted the semiconductor industry. His innovative patents and collaborations highlight his commitment to advancing technology. His contributions continue to influence the field and inspire future innovations.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]