The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2000

Filed:

Dec. 15, 1995
Applicant:
Inventors:

William Brearley, Poughkeepsie, NY (US);

Laertis Economikos, Wappingers Falls, NY (US);

Paul F Findeis, Glenham, NY (US);

Kimberley A Kelly, Poughkeepsie, NY (US);

Bouwe W Leenstra, Walden, NY (US);

Arthur Gilman Merryman, Hopewell Juction, NY (US);

Eric Daniel Perfecto, Poughkeepsie, NY (US);

Chandrika Prasad, Wappingers Falls, NY (US);

James Patrick Wood, Beacon, NY (US);

Roy Yu, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K / ;
U.S. Cl.
CPC ...
428119 ; 428131 ; 428156 ; 2281801 ; 22818021 ; 22818022 ; 228245 ; 228246 ; 2282481 ; 2282485 ;
Abstract

An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.


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