International Business Machines Corporation

Globalfoundries Inc.

General Wire & Stamping Company, Incorporated

Paul F Findeis

Roy Rongqing Yu

Laertis Economikos

Eric D Perfecto

Chandrika Prasad

Arthur Gilman Merryman

William Harrington Brearley

Kimberley A Kelly

Bouwe W Leenstra

James Patrick Wood

Mukta G Farooq

Kevin Shawn Petrarca

Richard Paul Volant

Charles Jesse Taft

Russell Herbert Arndt

Krystyna Waleria Semkow

Glen Nelson Biggs

Phillip W Palmatier

Renee L Weisman

Emanuele F Lopergolo

Karen P McLaughlin

John P Gauci

Minkailu A Jalloh

Thomas A Kelly

Kenneth R Idler

Victor M Vitek

John Di Santis

An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiOand SiNdeposited thereon, where the etching includes dissolving a quantity of the SiOand a quantity of the SiNin the first etchant. A quantity of insoluble SiOprecipitates. A ratio of a first etch rate of SiNto a first etch rate of SiOis determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of SiNto a second etch rate of SiOin the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.

Selective etching bath methods

A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.

Method of fabricating coaxial through-silicon via

An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiOand SiNdeposited thereon, where the etching includes dissolving a quantity of the SiOand a quantity of the SiNin the first echant. A quantity of insoluble SiOprecipitates. A ratio of a first etch rate of SiNto a first etch rate of SiOis determined to be less than a predetermined threshold. A portion of the first etchant is combined with a second etchant to form a conditioned etchant. A second plurality of silicon wafers is etched in the conditioned etchant. A ratio of a second etch rate of SiNto a second etch rate of SiOin the conditioned etchant is greater than the threshold. A method for exchanging an etching bath solution and a method for forming a selective etchant are also disclosed.

A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

Coaxial through-silicon via

An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

Apparatus and method for use in manufacturing semiconductor devices

A process for reworking of PGA chip carriers where one or more I/O pins is unplated. The process includes electrolytically etching the I/O pins which removes any corrosion product from the unplated I/O pins and removes the top gold layer from the remaining I/O pins. The etchant includes a metal-providing compound selected from the group consisting of a silver salt, copper cyanide, silver cyanide, gold cyanide or mixtures thereof, at a concentration in the range from about 2.7 to about 4.1 g/l as metal; potassium or sodium carbonate at a concentration in the range from about 10 to about 100 g/l; and potassium or sodium cyanide at a concentration in the range from about 29 to about 35 g/l.

Process of reworking pin grid array chip carriers

An apparatus for use in manufacturing a semiconductor device having input-output (IO) lands arranged in an IO array on an IO face includes a body having a plurality of cavities extending from an operating face into the body; the cavities are arranged in a cavity loci array which is in registeration with the IO lands when the apparatus is in a manufacturing position with the operating face generally adjacent the IO face. Each cavity has a depth and a lateral expanse which cooperate to establish a volume defined by a cavity bottom and at least one cavity wall. The volume accommodates an appropriate amount of solder material to establish a measure of the solder material on a facing IO land when the apparatus is in the manufacturing position. The depth is appropriate to facilitate wettingly attracting the solder material to the facing IO land when the apparatus is in the manufacturing position and the semiconductor device and the apparatus are exposed to appropriate ambient conditions to effect reflow of the solder material. The invention also includes a method for using the apparatus in manufacturing a semiconductor device.

Apparatus for providing solder interconnections to semiconductor and

Disclosed is a plating structure including a substrate having a plurality of pins to be plated and a metallic plating screen having a plurality of apertures, wherein each of the apertures has at least two tabs spaced apart from each other, wherein the metallic plating screen is placed over the pins so that at least two pins penetrate each aperture, each of the pins contacting a tab of the aperture. Also disclosed is a method of electrolytically plating a plurality of pins utilizing the above metallic plating screen.

Plating structure for a pin grid array package

An apparatus and a method for its use for plating pin grid array packaging modules, with a fixture capable of simultaneously holding a plurality of said pin grid array modules such that three-dimensional bottom surface metallurgy (BSM) is sealingly protected during plating of top surface metallurgy (TSM).

Apparatus and method for plating pin grid array packaging modules

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Verbank, NY, United States of America

Paul F Findeis