Patrick Edward Perry

This inventor holds 17 USPTO granted patents and 2 published patent applications, primarily in Low-Power Electronics. Top assignee: International Business Machines Corporation. Active years: 1993-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Patrick Edward Perry. Retrieved from https://idiyas.com/inventor/patrick-edward-perry

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 17 (Patent Applications = 2)

% Patents Active = 88.2

Average Co-Inventor Count = 3.4

ph-index = 9

Forward Citations = 316(Granted Patents)

Location History:

Colchester, VT (US) (1993 - 1994)
Essex Junction, VT (US) (1998 - 2004)
Shelburne, VT (US) (2000 - 2017)

Company Filing History:

17 out of 166,425

International Business Machines Corporation

patents

Years Active: 1993-2017

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Areas of Expertise:

Memory Testing

Error Correction

Low-Power Design

VLSI Circuits

Power Consumption

Voltage Rails

Digital Circuits

Power Reduction

Output Drivers

Circuit Design

Performance Optimization

Current Limiting

17 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9734920 - Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories (2017-08-15),

2. 9224503 - Memory test with in-line error correction code logic (2015-12-29),

3. 6880074 - In-line code suppression (2005-04-12),

4. 6802033 - Low-power critical error rate communications controller (2004-10-05),

5. 6711719 - Method and apparatus for reducing power consumption in VLSI circuit designs (2004-03-23),

6. 6678847 - Real time function view system and method (2004-01-13),

7. 6479974 - Stacked voltage rails for low-voltage DC distribution (2002-11-12),

8. 6477654 - Managing VT for reduced power using power setting commands in the instruction stream (2002-11-05),

9. 6317840 - Control of multiple equivalent functional units for power reduction (2001-11-13),

10. 6269468 - Split I/O circuit for performance optimization of digital circuits (2001-07-31),

11. 6097243 - Device and method to reduce power consumption in integrated (2000-08-01),

12. 6026224 - Redundant vias (2000-02-15),

13. 6011383 - Low powering apparatus for automatic reduction of power in active and (2000-01-04),

14. 5874833 - True/complement output bus for reduced simulataneous switching noise (1999-02-23),

15. 5784575 - Output driver that parks output before going tristate (1998-07-21),

Title: The Innovative Journey of Patrick Edward Perry

Introduction: Patrick Edward Perry, a visionary inventor hailing from Shelburne, VT (US), has made significant contributions to the field of technology with his groundbreaking inventions.

Latest Patents: Patrick Edward Perry's latest patents include cutting-edge technologies in renewable energy systems and sustainable agriculture practices, showcasing his commitment to creating a more environmentally friendly world.

Career Highlights: Throughout his illustrious career, Patrick Edward Perry has been recognized for his pioneering work in the development of advanced robotics for industrial applications, as well as his innovative solutions in the healthcare sector, improving patient care and treatment outcomes.

Collaborations: Patrick Edward Perry has collaborated with leading research institutions and universities to further his inventions, working closely with experts in various fields to bring his ideas to life. His partnerships with top companies have led to the successful commercialization of his inventions, benefiting industries worldwide.

Conclusion: In conclusion, Patrick Edward Perry stands as a beacon of innovation, continuously pushing the boundaries of what is possible through his inventive spirit and dedication to creating a better future for all. His impact on the world of technology and beyond is truly remarkable.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

2 patents pending: