The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2000

Filed:

Nov. 20, 1996
Applicant:
Inventors:

Laura Rohwedder Darden, Essex Junction, VT (US);

William John Livingstone, Cambridge, VT (US);

Jeannie Harrigan Panner, Underhill, VT (US);

Patrick Edward Perry, Essex Junction, VT (US);

William Frank Pokorny, Jericho, VT (US);

Paul Steven Zuchowski, Fletcher, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39550011 ; 39550009 ; 39550012 ;
Abstract

A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.


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