International Business Machines Corporation

Patrick Edward Perry

Sebastian Theodore Ventrone

Alvar Antonio Dean

Kenneth Joseph Goodnow

Wilbur David Pricer

Claude Louis Bertin

William R Tonti

David James Hathaway

Michael Richard Ouellette

John Maxwell Cohn

Scott Whitney Gould

Kevin William Gorman

Mark G Marshall

Paul Steven Zuchowski

Steven Frederick Oakland

William John Livingstone

Jeannie H Panner

Scott Alan Tetreault

Laura R Darden

Charles K Erdelyi

William F Pokorny

Amir H Farrahi

Thomas M Lepsic

William Robert Patrick Tonti

Bijit T Patel

John W Mathews

Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

Memory test with in-line error correction code logic

Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

In-line code suppression

A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

Low-power critical error rate communications controller

In integrated circuit (IC) designs, a component of power consumed may be represented as Power&equals;&frac12; FCV , where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.

Method and apparatus for reducing power consumption in VLSI circuit designs

A system and method for determining the operational state of a logic device having a plurality of shadow registers, each associated with one of a plurality of functional registers. Data stored in a functional register is, under selected conditions, also stored in an associated shadow register. These conditions include without limitation receipt by the functional register of predetermined event information such as an opcode, memory address or other information. Data in a given set of functional registers, e.g., registers making up pipeline stages in a microprocessor, may be stored in shadow registers simultaneously or sequentially when given data reaches a given register in the set. Additionally, data is stored in the shadow registers without interrupting execution cycles of the logic device.

Real time function view system and method

A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Stacked voltage rails for low-voltage DC distribution

An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.

Managing VT for reduced power using power setting commands in the instruction stream

A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.

Control of multiple equivalent functional units for power reduction

A logic circuit device and circuit design methodology includes a &ldquo;split-book&rdquo; logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using &ldquo;split&rdquo; book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting. Then, the output buffers may then be connected together according to criticality of the path and net capacitive load they are driving. Different split book input/output circuit combinations may be attempted during the design phase until an optimal tradeoff between power optimization and performance is reached.

Split I/O circuit for performance optimization of digital circuits

According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Device and method to reduce power consumption in integrated

A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

Redundant vias

A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.

Low powering apparatus for automatic reduction of power in active and

A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit. The ratio determining circuit further generates a true/complement (T/C) signal having a first state if it is determined that more than a prescribed percentage of bits are in transition, the T/C signal having a second state otherwise. Lastly, a circuit is provided for complementing the bits of the next state register in response to the T/C signal being in the first state, and not complementing the bits of the next state register in response to the T/C signal being in the second state, prior to being transferred into the current state register and output onto the bus during the next clock cycle.

True/complement output bus for reduced simulataneous switching noise

Disclosed is a tristate circuit driver capable of both parking the output in a deasserted state and switching to a tristate mode in less than one clock cycle. In a preferred embodiment, the driver circuitry utilized a delay device to generate a pulse signal immediately after the transition in an enable signal is detected. The pulse signal then causes the tristate driver to output a signal of a predetermined voltage for a duration of less then one clock cycle.

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Shelburne, VT, United States of America

Patrick Edward Perry