Paras Ajay

Title: Innovations of Paras Ajay

Introduction

Paras Ajay is a prominent inventor based in Austin, TX (US). He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work focuses on advanced methods for integrating components into compact devices, showcasing his expertise in innovative assembly processes.

Latest Patents

Among his latest patents, Paras Ajay has developed a method for the heterogeneous integration of components onto compact devices using moiré-based metrology and vacuum-based pick-and-place techniques. This assembly process utilizes a vacuum-based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques, resulting in highly accurate and parallel assembly of feedstocks. Another notable patent is for a nanoscale-aligned three-dimensional stacked integrated circuit. This method fabricates a 3D stacked integrated circuit using pick-and-place strategies to stack source wafers with device layers fabricated through standard two-dimensional semiconductor fabrication technologies. The source wafers can be stacked in various configurations, including face-to-face and back-to-back, with connections made using Through Silicon Vias (TSVs) or Inter Layer Vias (ILVs).

Career Highlights

Paras Ajay is affiliated with the University of Texas System, where he continues to push the boundaries of semiconductor innovation. His work has garnered attention for its potential applications in enhancing the performance and efficiency of electronic devices.

Collaborations

He collaborates with notable colleagues, including Sidlgata V Sreenivasan and Ovadia Abed, contributing to a dynamic research environment that fosters innovation.

Conclusion

Paras Ajay's contributions to semiconductor technology through his innovative patents and collaborative efforts position him as a key figure in the field. His work not only advances technology but also inspires future innovations in electronic device assembly.