The University of Texas System

Paras Ajay

Sidlgata V Sreenivasan

Ovadia Abed

Shrawan Singhal

Aseem Sayal

Mark McDermott

Lawrence R Dunn

Michael Cullinan

Akhila Mallavarapu

Jaydeep Kulkarni

Praveen Joseph

Michelle Grigas

Vipul Goyal

Anshuman Cherala

Lawrence A Dunn

Ofodike A Ezekoye

A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Heterogeneous integration of components onto compact devices using moiré based metrology and vacuum based pick-and-place

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Nanoscale-aligned three-dimensional stacked integrated circuit

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

Nanofabrication and design techniques for 3D ICs and configurable ASICs

A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

Roll-to-roll programmable film imprint lithography

A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Heterogeneous integration of components onto compact devices using moire based metrology and vacuum based pick-and-place

Techniques for delivering sub-5 nm overlay control over multiple fields. One such technique reduces overlay from the wafer side using wafer-thermal actuators. In another technique, the topology of the template is optimized so that the inter-field mechanical coupling between fields in the multi-field template is reduced thereby allowing overlay to be simultaneously reduced in multiple fields in the template. A further technique combines the wafer-thermal and template actuation techniques to achieve significantly improved single and multi-field overlay performance.

Multi-field overlay control in jet and flash imprint lithography

Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

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Austin, TX, United States of America

Paras Ajay