The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2024
Filed:
Dec. 14, 2022
Board of Regents, the University of Texas System, Austin, TX (US);
Sidlgata V. Sreenivasan, Austin, TX (US);
Paras Ajay, Austin, TX (US);
Aseem Sayal, Austin, TX (US);
Ovadia Abed, Austin, TX (US);
Mark McDermott, Austin, TX (US);
Jaydeep Kulkarni, Austin, TX (US);
Shrawan Singhal, Austin, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).