Andhra Pradesh, India

Palle Sundar Veerendranath

This inventor holds 7 USPTO granted patents and 3 published patent applications. Top assignee: Globalfoundries U.S. Inc.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Palle Sundar Veerendranath. Retrieved from https://idiyas.com/inventor/palle-sundar-veerendranath

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 7 

% Patents Active = 100.0

Average Co-Inventor Count = 4.1

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2025-2026

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7 patents (USPTO):Explore Patents

Title: Palle Sundar Veerendranath: Innovator in Power Electronics

Introduction

Palle Sundar Veerendranath is a notable inventor based in Andhrapradesh, India. He has made significant contributions to the field of power electronics, holding a total of 7 patents. His innovative designs focus on enhancing the efficiency and functionality of power management systems.

Latest Patents

One of his latest patents is a high voltage power switch. This power switch includes a PFET with a gate, a source coupled to a source voltage, and a drain for outputting a supply voltage. Additionally, it features a level shifter that has an input node for receiving an input voltage, which includes first and second voltage levels. The supply node receives the supply voltage, which includes third and fourth voltage levels. The output node is responsible for outputting an output voltage, coupled to the gate of the PFET. When the input voltage is at the first voltage level, the output voltage is also at the first voltage level, allowing the PFET to be in a conducting state. Importantly, the voltage between the gate and drain of the PFET, as well as the voltage between the gate and source of the FET, do not exceed the maximum voltage of the PFET.

Another significant patent is a charge pump circuit with parallel charge pump stages. This circuit includes a single primary charge pump stage or multiple primary charge pump stages connected in series. A pass transistor is connected between the output node of the primary charge pump stage and an output terminal. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to minimize ripple, with its size selected to achieve a desired balance between the amount of ripple and circuit size.

Career Highlights

Palle Sundar Veerendranath is currently employed at GlobalFoundries U.S. Inc., where he continues to innovate in the field of power electronics. His work has been instrumental in developing advanced technologies that improve power management systems.

Collaborations

He has collaborated with notable coworkers such as Siva Kumar Chinthu and Abdul Rajak, contributing to various projects that enhance the capabilities of their technologies.

Conclusion

Palle Sundar Veerendranath

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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