The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jan. 26, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Siva Kumar Chinthu, Bangalore, IN;

Suresh Pasupula, Bangalore, IN;

Sheikh Sabiq Chishti, Manipur, IN;

Palle Sundar Veerendranath, Bangalore, IN;

Sreedevi Bindu, Bangalore, IN;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0026 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01);
Abstract

A multiplexing circuit for a memory, including: a first parallel branch for coupling a program voltage to a first bitline corresponding to a first bit cell of the memory during a program mode of the memory; and a second parallel branch for coupling a program inhibit voltage to a plurality of additional bitlines corresponding to a plurality of additional bit cells of the memory during a program inhibit mode of the memory, wherein the first parallel branch couples an erase inhibit voltage to the plurality of additional bitlines during an erase inhibit mode of the memory, and wherein the second parallel branch couples an erase voltage to the first bitline during an erase mode of the memory.


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