Nikhil Mazumder

Title: Nikhil Mazumder: Innovator in FPGA Architecture

Introduction

Nikhil Mazumder is a prominent inventor based in San Jose, CA (US). He has made significant contributions to the field of FPGA architecture, holding a total of 6 patents. His innovative work focuses on enhancing clock distribution and timing mechanisms within FPGA systems.

Latest Patents

One of Nikhil's latest patents is a Delay Locked Loop (DLL) for an FPGA architecture. This DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback. It achieves this by adding additional delay to the feedback clock, aligning it with the reference clock at one cycle later. The design includes a 0 ns clock-to-out mode, which accounts for an input buffer in the feedback path. Additionally, the feedback clock can be doubled by a clock doubler with a 50% duty cycle adjustment integrated into the feedback path. Flexible timing is achieved by aligning the reference clock to the feedback clock using additional delay elements in both the feedback and reference clock paths.

Career Highlights

Nikhil has worked with notable companies, including Actel Corporation, Inc. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking innovations in the field of FPGA technology.

Collaborations

Throughout his career, Nikhil has collaborated with esteemed colleagues such as William C. Plants and Arunangshu Kundu. These partnerships have fostered a creative environment that has led to significant advancements in their projects.

Conclusion

Nikhil Mazumder is a distinguished inventor whose work in FPGA architecture has led to multiple patents and innovative solutions. His contributions continue to influence the field and inspire future advancements in technology.