Actel Corporation, Inc.

Other

Intel Corporation

Nikhil Mazumder

William C Plants

Arunangshu Kundu

James Dean Joseph

Wayne W Wong

Sung-Soo Cho

Diane M Bryant

Farid Rastgar

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.

Delay locked loop for an FPGA architecture

Delay locked loop for and FPGA architecture

In an integrated circuit comprising discrete circuit modules, dedicated test signals for the individual circuit modules are multiplexed with operational signals to the external pins of the integrated circuit. When not in a test mode, the external pins of the chip are coupled to the normal operational signals. When a test mode is commanded, certain external pins are coupled to test signals that are not otherwise available off-chip in accordance with the contents of a test register.

Method and apparatus for mapping test signals of an integrated circuit

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San Jose, CA, United States of America

Nikhil Mazumder