Minas Gerais, Brazil

Mirlaine Aparecida Crepalde

This inventor holds 3 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2019-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mirlaine Aparecida Crepalde. Retrieved from https://idiyas.com/inventor/mirlaine-aparecida-crepalde

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 8.2

ph-index = 2

Forward Citations = 10(Granted Patents)


Location History:

  • Belo Horizonte, BR (2019)
  • Belo Horizonte, BZ (2020)
  • Minas Gerais, BR (2021)

Company Filing History:


Years Active: 2019-2021

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3 patents (USPTO):Explore Patents

Title: Mirlaine Aparecida Crepalde: Innovator in Electronic Design Verification

Introduction

Mirlaine Aparecida Crepalde is a notable inventor based in Minas Gerais, Brazil. She has made significant contributions to the field of electronic design verification, holding a total of 3 patents. Her work focuses on improving methods and systems for verifying electronic designs, which is crucial in the development of reliable electronic circuits.

Latest Patents

One of her latest patents is titled "System, method, and computer program product for determining suitability for formal verification." This patent describes a method for electronic design verification that involves using a processor to receive an electronic design and providing it to a machine learning engine. The method automatically determines whether the electronic design is suitable for formal verification based on the output of the machine learning engine.

Another significant patent is "System, method, and computer program product for over-constraint/deadcode detection in a formal verification." This invention relates to a method used in the formal verification of electronic circuits. It includes receiving a portion of an electronic circuit design and analyzing its syntactic structure. The method generates a parse tree and identifies conditional nodes, which are then displayed on a graphical user interface prior to synthesis.

Career Highlights

Mirlaine is currently employed at Cadence Design Systems, Inc., where she continues to innovate in the field of electronic design. Her expertise in formal verification and electronic circuit design has positioned her as a valuable asset in her company.

Collaborations

Throughout her career, Mirlaine has collaborated with talented individuals such as Ronalu Augusta Nunes Barcelos and Hudson Dyele Pinheiro De Oliveira. These collaborations have further enriched her work and contributed to advancements in electronic design verification.

Conclusion

Mirlaine Aparecida Crepalde is a pioneering inventor whose work in electronic design verification has led to significant advancements in the field. Her patents reflect her commitment to improving the reliability of electronic circuits, making her a key figure in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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