The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
May. 25, 2018
Cadence Design Systems, Inc., San Jose, CA (US);
Luis Humberto Rezende Barbosa, Belo Horizonte, BZ;
Raquel Lara dos Santos Pereira, Belo Horizonte, BZ;
Caio Alves Furtado, Belo Horizonte, BZ;
Breno Augusto Dias Vitorino, Belo Horizonte, BZ;
Mirlaine Aparecida Crepalde, Belo Horizonte, BZ;
Rodrigo da Silva Mantini Viana, Belo Horizonte, BZ;
Lucas Duarte Prates, Belo Horizonte, BZ;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.