Cadence Design Systems, Inc.

Mirlaine Aparecida Crepalde

Georgia Penido Safe

Vincent Gregory Reynolds

Yumi Monma

Guilherme Henrique De Sousa Santos

Raquel Lara Dos Santos Pereira

Felipe Althoff

Regina Mara Amaral Fonseca

Fernanda Augusta Braga

Ronalu Augusta Nunes Barcelos

Lucas Martins Chaves

Lucas Duarte Prates

Mariana Ferreira Marques

Hudson Dyele Pinheiro De Oliveira

Lucas Luz Reckziegel

Glauber Tadeu De Sousa Carmo

Augusto Amaral Mafra

Valdir Antoniazzi Júnior

Luis Humberto Rezende Barbosa

Caio Alves Furtado

Breno Augusto Dias Vitorino

Pedro Bruno Neri Silva

Rodrigo Da Silva Mantini Viana

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.

System, method, and computer program product for over-constraint/deadcode detection in a formal verification

The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.

System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design

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Minas Gerais, Brazil

Mirlaine Aparecida Crepalde