Ming-Chyuan Chen

Title: Innovations by Ming-Chyuan Chen in Circuit Design

Introduction

Ming-Chyuan Chen is a notable inventor based in San Jose, CA, who has made significant contributions to the field of circuit design. With a total of four patents to his name, Chen's work focuses on enhancing the efficiency of circuit designs, particularly in reducing dynamic power consumption.

Latest Patents

Chen's latest patents include innovative methodologies for circuit design systems that replace traditional flip-flops with pulsed latches. These designs aim to create circuits that consume less dynamic power. The methodology involves modifying an initial circuit design that includes a clock network coupled to edge-triggered flip-flops. By generating a modified circuit design that utilizes pulsed latches driven by pulse generators, Chen's approach significantly reduces power consumption. Furthermore, the design methodology incorporates the addition of delay cells to balance the clock network and compensate for timing effects caused by the insertion of pulse generators. It also includes cloning forbidden clock paths to increase the number of flip-flops eligible for pulsed latch replacement.

Career Highlights

Ming-Chyuan Chen is currently employed at Cadence Design Systems, Inc., where he continues to innovate in the field of integrated circuit design. His work has been instrumental in advancing methodologies that enhance circuit efficiency and performance.

Collaborations

Chen collaborates with talented individuals such as Hung-Chun Li and KunMing Ho, contributing to a dynamic work environment that fosters innovation and creativity.

Conclusion

Ming-Chyuan Chen's contributions to circuit design through his innovative patents demonstrate his commitment to advancing technology in the field. His work not only enhances circuit efficiency but also sets a precedent for future innovations in power consumption reduction.