Cadence Design Systems, Inc.

Ming-Chyuan Chen

Hung-Chun Li

KunMing Ho

Chien-Chu Kuo

Minghorng Lai

A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.

Circuit design systems for replacing flip-flops with pulsed latches

Integrated circuit design systems for replacing flip-flops with pulsed latches

System and method of replacing flip-flops with pulsed latches in circuit designs

Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-based clock tree estimation, wherein each block is subdivided into one or more grids. The aspects further include merging of the estimated block-level clock tree structures with the top-level clock tree synthesis.

Method and system for clock tree synthesis of an integrated circuit

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San Jose, CA, United States of America

Ming-Chyuan Chen