The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
Oct. 27, 2005
Hung-chun LI, San Jose, CA (US);
Chien-chu Kuo, San Jose, CA (US);
Minghorng Lai, Cupertino, CA (US);
Ming-chyuan Chen, San Jose, CA (US);
Hung-Chun Li, San Jose, CA (US);
Chien-Chu Kuo, San Jose, CA (US);
Minghorng Lai, Cupertino, CA (US);
Ming-Chyuan Chen, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-based clock tree estimation, wherein each block is subdivided into one or more grids. The aspects further include merging of the estimated block-level clock tree structures with the top-level clock tree synthesis.