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For the Inventor, By the Inventor

Allen, TX, United States of America

Matthew B Smittle

This inventor holds 16 USPTO granted patents and 1 published patent application, primarily in Memory Circuit Design. Top assignees: Cadence Design Systems, Inc., Oracle America, Inc., Oracle International Corporation. Active years: 2013-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Matthew B Smittle. Retrieved from https://idiyas.com/inventor/matthew-b-smittle

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 16 

% Patents Active = 100.0

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 45(Granted Patents)


Company Filing History:

goldMedal5 out of 2,620 
 
Cadence Design Systems, Inc.
 patents
silverMedal5 out of 1,928 
 
Oracle America, Inc.
 patents
bronzeMedal3 out of 11,917 
 
Oracle International Corporation
 patents
4. 3 out of 5,432 
 
Western Digital Technologies, Inc.
 patents

Years Active: 2013-2024

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Areas of Expertise:
Memory Circuit
Cache Management
Debug Techniques
Processor Optimization
Instruction Handling
Thread Management
Dependency Matrix
Debug Command Execution
Error Handling
Stalling Mitigation
Unified Pick Queue
High-Frequency Circuits
16 patents (USPTO):Explore Patents
1. 12182016 - Memory circuit with power registers (2024-12-31),
2. 12141474 - Queue circuit for controlling access to a memory circuit (2024-11-12),
3. 11960400 - Managing multiple cache memory circuit operations (2024-04-16),
4. 11740973 - Instruction error handling (2023-08-29),
5. 11537505 - Forced debug mode entry (2022-12-27),
6. 11119149 - Debug command execution using existing datapath circuitry (2021-09-14),
7. 11086631 - Illegal instruction exception handling (2021-08-10),
8. 11023342 - Cache diagnostic techniques (2021-06-01),
9. 10740102 - Hardware mechanism to mitigate stalling of a processor core (2020-08-11),
10. 10430342 - Optimizing thread selection at fetch, select, and commit stages of processor core pipeline (2019-10-01),
11. 9286075 - Optimal deallocation of instructions from a unified pick queue (2016-03-15),
12. 9262171 - Dependency matrix for the determination of load dependencies (2016-02-16),
13. 9086890 - Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated (2015-07-21),
14. 9058180 - Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions (2015-06-16),
15. 8504805 - Processor operating mode for mitigating dependency conditions between instructions having different operand sizes (2013-08-06),

Title: The Innovative Journey of Matthew B Smittle

Introduction: Matthew B Smittle, a talented inventor based in Allen, Texas, has made significant contributions to the field of technology through his creative and groundbreaking inventions.

Latest Patents: Matthew B Smittle holds several patents in various technological domains, showcasing his versatility and ingenuity in the innovation landscape.

Career Highlights: With a career spanning over two decades, Matthew B Smittle has consistently demonstrated his passion for innovation and problem-solving. His dedication to pushing the boundaries of technology has led to the development of cutting-edge solutions that have positively impacted numerous industries.

Collaborations: Throughout his career, Matthew B Smittle has collaborated with leading tech companies, research institutions, and universities to further enhance his inventions and bring them to market. His collaborative spirit has been instrumental in driving innovation forward.

Conclusion: Matthew B Smittle's relentless pursuit of innovation and his commitment to creating solutions that make a difference highlight him as a visionary inventor in the ever-evolving tech landscape. His contributions continue to inspire and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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