The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Jan. 31, 2019
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Jama I. Barreh, Austin, TX (US);

Robert T. Golla, Austin, TX (US);

Thomas M. Wicki, Palo Alto, CA (US);

Matthew B. Smittle, Allen, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/263 (2006.01); G06F 9/30 (2018.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G06F 11/263 (2013.01); G06F 9/30101 (2013.01); G06F 11/2736 (2013.01);
Abstract

Techniques are disclosed relating to cache debug using control registers based on debug commands. In some embodiments, an apparatus includes a processor core, debug circuitry, and control circuitry. In some embodiments, the debug circuitry is configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the control circuitry is configured to, in response to an abstract command to read data from the cache: write cache address information to a first control register, assert a trigger signal to cause a read of the data from the cache to a second control register, based on the cache address information in the first control register, and send data from the second control register to the debug circuitry. In various embodiments, this may facilitate hardware cache debug using debug circuitry that also controls software debugging.


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