The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2022
Filed:
Feb. 10, 2021
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Robert T. Golla, Austin, TX (US);
Matthew B. Smittle, Allen, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/36 (2006.01); G06F 11/30 (2006.01); G06F 11/07 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3656 (2013.01); G06F 11/0757 (2013.01); G06F 11/1474 (2013.01); G06F 11/3027 (2013.01); G06F 11/366 (2013.01); G06F 11/3664 (2013.01);
Abstract
The present disclosure is directed to a mechanism for forcing a processor to enter a debug mode. In one embodiment, a processor includes a logic circuit configured to receive a halt request. In response to receiving the halt request while the processor is not in a quiescent state, the logic circuit forces the processor into the quiescent state after a threshold amount of time has elapsed. Processor operation is then halted, and the processor thus becomes accessible for a debugger to perform debug operations.