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For the Inventor, By the Inventor

Boise, ID, United States of America

Leland R Nevill

USPTO Granted Patents = 58

Average Co-Inventor Count = 3.0

ph-index = 21

Forward Citations = 1,213(Granted Patents)

Forward Citations (Not Self Cited) = 1,163(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal56 out of 38,002 
 
Micron Technology Incorporated
 patents
silverMedal2 out of 832,880 
Other
 patents

Years Active: 1989-2016

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Areas of Expertise:
Error Detection
Integrated Circuits
Memory Management
Data Compression
Semiconductor Testing
Chip Package Alignment
Self-Test Circuits
Environmental Testing
Memory Devices
Short-Circuited Isolation
Terminal Testing
Surge Capacitors
58 patents (USPTO):Explore Patents
1. 9483370 - Error detection/correction based memory management (2016-11-01),
2. 7567091 - Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2009-07-28),
3. RE40623 - Method and apparatus for identifying integrated circuits (2009-01-19),
4. 7323896 - Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2008-01-29),
5. 7315179 - System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2008-01-01),
6. 7276927 - Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2007-10-02),
7. 7276926 - Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2007-10-02),
8. 7212020 - Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2007-05-01),
9. 7034561 - Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2006-04-25),
10. RE38956 - Data compression circuit and method for testing memory devices (2006-01-30),
11. 6858453 - Integrated circuit package alignment feature (2005-02-22),
12. 6852999 - Reduced terminal testing system (2005-02-08),
13. 6836003 - Integrated circuit package alignment feature (2004-12-28),
14. 6831475 - Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer (2004-12-14),
15. 6815968 - Reduced terminal testing system (2004-11-09),

Title: The Innovative Journey of Leland R Nevill

Introduction: Leland R Nevill, a pioneering inventor based in Boise, ID, has made significant contributions to the field of technology with his inventive spirit and dedication to innovation.

Latest Patents: Leland R Nevill holds several patents in various technological domains, showcasing his versatility and creativity in inventing new solutions to complex problems.

Career Highlights: Throughout his illustrious career, Leland R Nevill has been at the forefront of technological advancements, leading groundbreaking projects and pushing the boundaries of innovation.

Collaborations: Leland R Nevill has collaborated with top research institutions, leading companies, and brilliant minds in the industry, fostering a culture of innovation and knowledge sharing.

Conclusion: In conclusion, Leland R Nevill's passion for innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of inventors, leaving a lasting impact on the technological landscape.

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