Micron Technology Incorporated

Other

Leland R Nevill

Warren M Farnworth

Eugene H Cloud

Raymond J Beffa

William K Waller

Ray J Beffa

Jerrold L King

Kevin G Duesman

David J Corisis

Daniel Cram

Tracy V Reynolds

Gary M Johnson

Michael R Slaughter

Gregory A Barnett

Ward D Parkinson

Gary R Gilliam

Thomas M Trent

Stanley N Protigal

Wen-Foo Chern

Steven L Hamren

Bruce J Ford

William C Layer

Ken Waller

Gene Cloud

Than Huu Nguyen

Neil L Hansen

Mark A Tverdy

Cory J Reche

Timothy F Martin

Web-Foo Chern

Eugen H Cloud

The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Error detection/correction based memory management

A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic identification information. The integrated circuit also includes an optical identification mark displaying a machine-readable optical identification code which corresponds with the electronic identification information stored in the identification circuit. The data encoded in the optical identification code may be identical with that of the electronic identification information. Alternatively, a look-up table or other correlating means may be employed to associate the optical identification code with the electronic identification information. The integrated circuit is packaged in a housing, and another optical identification mark is placed on an external surface of the housing. This second optical identification mark displays a machine-readable optical identification code which is identical or correlated to the electronic identification information stored in the identification circuit and/or the optical identification code displayed by the optical identification mark on the integrated circuit. Consequently, convenient and traceable identification of individual integrated circuits is provided during and after manufacture.

Method and apparatus for identifying integrated circuits

Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

System for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer

A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.

Data compression circuit and method for testing memory devices

An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semicircle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Integrated circuit package alignment feature

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer. In a preferred embodiment, the conductive path simultaneously carries a VCC power signal and the alternating signal to the circuitry. However, the alternating signal may be carried on a conductive path different from the one carrying the VCC signal. A great deal of information may be conveyed through the alternating signal, making other signals unnecessary in controlling, testing, stressing, and repairing dice on the wafer. For example, clocking information may be conveyed through the alternating signal. The circuitry may be placed in different modes in response to different characteristics of the alternating signal. The alternating signal and a VCC power signal are received through a single contact on each die. A wafer mode controlling system includes a system controller to control application of the alternating signals and other signals to the dice on the wafer. The semiconductor wafer mode controlling system may also control a probe positioning controller including an array of probes that selectively brings the probes into contact with the probe pads, whereby the alternating signal having the certain characteristics is transmitted from the probe to the circuitry through the probe pad and conductive path and the circuitry of each of the dice is placed into the mode.

Reduced terminal testing system

A semiconductor wafer having dice that include circuitry that is placed into a mode when the circuitry receives an alternating signal having certain characteristics. The alternating signal may be supplied from a system controller through a probe, probe pad, and conductive path on the wafer.

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Boise, ID, United States of America

Leland R Nevill