Lee Doyle Whetsel

This inventor holds 865 USPTO granted patents and 36 published patent applications and 5 EPO patents, primarily in Semiconductor Testing (CPC class G01R31-3177). Top assignees: Texas Instruments Corporation, Texas Instruments Incororated, Other. Active years: 1989-2026.

USPTO Granted Patents = 865 (Patent Applications = 36)

% Patents Active = 66.9

EPO Patents = 5

Average Co-Inventor Count = 1.1

ph-index = 32

Forward Citations = 4,778(Granted Patents)

Forward Citations (Not Self Cited) = 2,456(Dec 10, 2025)

Inventors with similar research interests:

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Location History:

Plano, TX (US) (1989 - 2008)
Allen, TX (US) (1998 - 2012)
Parker, TX (US) (2003 - 2024)

Company Filing History:

862 out of 29,845

Texas Instruments Corporation

patents

1 out of 1

Texas Instruments Incororated

patent

2 out of 834,350

Other

patents

Years Active: 1989-2026

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Areas of Expertise:

Through-Silicon Via

JTAG Operations

3D Stacked Die

Interposer Circuit

Scan Testing

Test Access Port

Device Access Port

Programmable Test Compression

Shadow Access Port

Wafer Scale Testing

Integrated Circuit

Test Compression Architecture

865 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12699134 - Addressable test access port (2026-08-04),

2. 12650466 - Interface to full and reduced pin JTAG devices (2026-06-09),

3. 12571840 - Array of through-silicon via contact points on a semiconductor die (2026-03-10),

4. 12540974 - Multiple access port circuits (2026-02-03),

5. 12467971 - Scan testing using scan frames with embedded commands (2025-11-11),

6. 12461148 - 3D stacked die test architecture (2025-11-04),

7. 12416670 - Falling clock edge JTAG bus routers (2025-09-16),

8. 12379393 - Testing interposer method and apparatus (2025-08-05),

9. 12352814 - Interposer circuit (2025-07-08),

10. 12313667 - Integrated circuit die test architecture (2025-05-27),

11. 12210060 - Device access port selection (2025-01-28),

12. 12188980 - Test access port with address and command capability (2025-01-07),

13. 12181521 - At-speed test access port operations (2024-12-31),

14. 12164001 - 3D tap and scan port architectures (2024-12-10),

15. 12163998 - TSV testing (2024-12-10),

Title: The Innovative Contributions of Lee Doyle Whetsel

Introduction

Lee Doyle Whetsel is a prominent inventor based in Parker, Texas, known for his significant contributions to technology and engineering. With an impressive portfolio of 860 patents, Whetsel has made a lasting impact in his field. His work primarily focuses on advancements in testing architectures and circuit designs.

Latest Patents

Among his latest patents is the "3D Stacked Die Test Architecture." This innovation describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The architecture utilizes an improved TAP design to facilitate the testing of parallel test circuits within the die. Another notable patent is the "Falling Clock Edge JTAG Bus Routers." This invention includes a controller with an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, and various outputs for shift and update registers. The design enhances the efficiency of testing processes in integrated circuits.

Career Highlights

Whetsel has had a distinguished career, working with renowned companies such as Texas Instruments Corporation. His expertise and innovative mindset have allowed him to contribute to various projects that push the boundaries of technology.

Collaborations

Throughout his career, Whetsel has collaborated with talented individuals, including Baher S. Haroun and Richard L. Antley. These partnerships have fostered a creative environment that has led to groundbreaking advancements in their respective fields.

Conclusion

Lee Doyle Whetsel's contributions to technology through his numerous patents and collaborations highlight his role as a leading inventor. His innovative spirit continues to inspire future generations in the field of engineering and technology.