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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12181521 B1

PDFFull Text
Date of Patent:
Dec. 31, 2024

Filed:

Nov. 02, 2023

At-speed test access port operations

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Lee D. Whetsel, Parker, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Carl G. Peterson

Frank D. Cimino

Primary Examiner:

Cynthia Britt

Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G06F 11/26 (2006.01); H10K 50/814 (2023.01); H10K 50/816 (2023.01); H10K 50/844 (2023.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01); H01L 27/12 (2006.01); H10K 59/12 (2023.01); H10K 102/00 (2023.01); H10K 102/10 (2023.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01); G06F 11/26 (2013.01); H10K 50/814 (2023.02); H10K 50/816 (2023.02); H10K 50/844 (2023.02); H10K 59/1213 (2023.02); H10K 59/122 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H10K 59/1201 (2023.02); H10K 2102/00 (2023.02); H10K 2102/103 (2023.02);
Abstract

In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

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