The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 29, 2024
Filed:
Apr. 17, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Lee D. Whetsel, Parker, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/28 (2006.01); G01R 31/302 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31713 (2013.01); G01R 31/2815 (2013.01); G01R 31/2884 (2013.01); G01R 31/3025 (2013.01); G01R 31/31703 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/3177 (2013.01); G01R 31/318558 (2013.01); G01R 31/2851 (2013.01);
Abstract
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (), only reduced pin JTAG devices (), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface () between the substrate () and a JTAG controller (). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.