The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2025
Filed:
May. 08, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Lee D. Whetsel, Parker, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); B05C 21/00 (2006.01); B44D 3/12 (2006.01); G01R 1/04 (2006.01); G01R 31/26 (2020.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
G01R 1/0416 (2013.01); B05C 21/00 (2013.01); B44D 3/126 (2013.01); G01R 31/26 (2013.01); G01R 31/2853 (2013.01); G01R 31/2889 (2013.01); G01R 31/3177 (2013.01); G01R 31/318538 (2013.01); H05K 1/115 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/17181 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01);
Abstract
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.