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Hsinchu, Taiwan

Kuei-Ying Lee

This inventor holds 9 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1996-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuei-Ying Lee. Retrieved from https://idiyas.com/inventor/kuei-ying-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9

% Patents Active = 88.9

Average Co-Inventor Count = 3.7

ph-index = 7

Forward Citations = 182(Granted Patents)

Location History:

Kaohsiung, TW (1999)
Chu-Tung, TW (2000)
Chu-Dong, TW (2000 - 2001)
Hsin-chu, TW (1996 - 2004)

Company Filing History:

9 out of 42,810

Taiwan Semiconductor Manufacturing Comp. Ltd.

Years Active: 1996-2004

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9 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6808985 - Products derived from embedded flash/EEPROM products (2004-10-26),

2. 6350662 - Method to reduce defects in shallow trench isolations by post liner anneal (2002-02-26),

3. 6214698 - Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer (2001-04-10),

4. 6129091 - Method for cleaning silicon wafers with deep trenches (2000-10-10),

5. 6110793 - Method for making a trench isolation having a conformal liner oxide and (2000-08-29),

6. 6046062 - Method to monitor the kink effect (2000-04-04),

7. 6015757 - Method of oxide etching with high selectivity to silicon nitride by (2000-01-18),

8. 5930644 - Method of forming a shallow trench isolation using oxide slope etching (1999-07-27),

9. 5521119 - Post treatment of tungsten etching back (1996-05-28),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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