Berkeley, CA, United States of America

Krste Asanovic

This inventor holds 24 USPTO granted patents and 9 published patent applications and 5 EPO patents, primarily in Secure Processor Architectures. Top assignees: Sifive, Inc., International Computer Science Institute. Active years: 1998-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Krste Asanovic. Retrieved from https://idiyas.com/inventor/krste-asanovic

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.1

ph-index = 1

Forward Citations = 41(Granted Patents)


Location History:

  • Berkeley, CA (US) (1998 - 2024)
  • Oakland, CA (US) (2024)

Company Filing History:


Years Active: 1998-2026

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Areas of Expertise:
Secure Control Flow
Vector Processing
Fault Tolerance
Memory Protection
Register Renaming
Pipelined Architectures
Error Management
Macro-op Fusion
Indirection Handling
Address Encoding
Event Recognition
Memory Caches
24 patents (USPTO):Explore Patents

Title: The Innovations of Krste Asanovic

Introduction

Krste Asanovic is a prominent inventor based in Berkeley, California. He has made significant contributions to the field of computer science and engineering, holding a total of 18 patents. His work focuses on advanced memory processing techniques and interconnect systems, which are crucial for modern computing.

Latest Patents

One of his latest patents is titled "Efficient processing of masked memory accesses." This patent discloses systems and methods for processing masked memory accesses, including handling fault exceptions and checking memory attributes of memory regions to be accessed. The implementation performs a two-level memory protection violation scheme for masked vector memory instructions. The first level memory check ignores mask information associated with a masked vector memory instruction and operates on a memory footprint associated with the instruction. If a memory protection violation is detected, a second level memory check evaluates mask information at a vector element level to determine whether a fault exception should be raised.

Another notable patent is for "Technologies for interconnect address remapper with event recognition and register management." This patent describes systems and methods for a configurable interconnect address remapper with event detection. An integrated circuit can include a processor core configured to execute instructions, along with region registers defined by a From Address range and a To Address. The interconnect address remapper translates an address associated with a transaction using the defined region registers, enhancing the efficiency of data processing.

Career Highlights

Krste Asanovic has worked with several notable companies, including SiFive, Inc. and the International Computer Science Institute. His experience in these organizations has allowed him to develop and refine his innovative ideas in the field of computer architecture and memory systems.

Collaborations

Throughout his career, Asanovic has collaborated with talented individuals such as Andrew Waterman and Joshua R Smith. These collaborations have contributed to the advancement of technology and the development of new ideas in the industry.

Conclusion

Krste Asanovic's contributions to the field of computer science through his patents and collaborations highlight his role as a leading inventor. His work continues to influence advancements in memory processing and interconnect systems, shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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