The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Jan. 15, 2023
Applicant:

Sifive, Inc., San Mateo, CA (US);

Inventors:

Murali Vijayaraghavan, San Mateo, CA (US);

Krste Asanovic, Berkeley, CA (US);

Assignee:

SiFive, Inc., San Mateo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 9/30047 (2013.01); G06F 9/321 (2013.01); G06F 11/0772 (2013.01); G06F 11/3024 (2013.01); G06F 11/3037 (2013.01); G06F 12/1027 (2013.01);
Abstract

Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.


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