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For the Inventor, By the Inventor

Boise, ID, United States of America

Koustav Sinha

USPTO Granted Patents = 15 

Average Co-Inventor Count = 2.9

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:

goldMedal14 out of 37,950 
 
Micron Technology Incorporated
 patents
where one patent can have more than one assignee

Years Active: 2021-2025

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15 patents (USPTO):Explore Patents
1. 12341110 - Methods and apparatus for using structural elements to improve drop/shock resilience in semiconductor devices (2025-06-24),
2. 12269106 - Two-step solder-mask-defined design (2025-04-08),
3. 12218079 - Semiconductor devices with reinforced substrates (2025-02-04),
4. 12211822 - Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods (2025-01-28),
5. 12211814 - Semiconductor interconnect structures with conductive elements, and associated systems and methods (2025-01-28),
6. 11908803 - Semiconductor devices with flexible connector array (2024-02-20),
7. 11869862 - Microelectronic components including metal pillars secured to bond pads, and related methods, assemblies, and systems (2024-01-09),
8. 11769752 - Stacked semiconductor die assemblies with substrate heat sinks and associated systems and methods (2023-09-26),
9. 11728307 - Semiconductor interconnect structures with conductive elements, and associated systems and methods (2023-08-15),
10. 11664360 - Circuit board with spaces for embedding components (2023-05-30),
11. 11646286 - Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints (2023-05-09),
12. 11552029 - Semiconductor devices with reinforced substrates (2023-01-10),
13. 11348875 - Semiconductor devices with flexible connector array (2022-05-31),
14. 11276659 - Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements (2022-03-15),
15. 11207744 - Two-step solder-mask-defined design (2021-12-28),

Title: Koustav Sinha: Innovator in Semiconductor Technology

Introduction

Koustav Sinha is a prominent inventor based in Boise, ID (US). He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work focuses on improving the resilience of semiconductor devices against mechanical shocks.

Latest Patents

Among his latest patents is a method and apparatus for using structural elements to enhance drop and shock resilience in semiconductor devices. This innovative semiconductor package assembly features a first mounting surface of a package substrate that faces a second mounting surface of a printed circuit board. A first structural element bond pad is mounted to the first mounting surface, while a second structural element bond pad is mounted to the second mounting surface, ensuring alignment between the two. A structural element is interconnected with solder joints to both bond pads, effectively absorbing mechanical shock when a compressive force is applied. Another notable patent is the two-step solder-mask-defined design for a BGA package, which includes a pad mounted on a substrate and a solder resist layer with aligned apertures to create a solder-mask-defined mounting pad.

Career Highlights

Koustav Sinha is currently employed at Micron Technology Incorporated, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the reliability and performance of semiconductor devices.

Collaborations

He has collaborated with notable coworkers such as Shams U Arifeen and Christopher Glancey, contributing to various projects that enhance the capabilities of semiconductor technologies.

Conclusion

Koustav Sinha's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work not only improves device resilience but also sets the stage for future advancements in semiconductor applications.

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