Ama, Japan

Koji Matsuo

This inventor holds 3 USPTO granted patents. Top assignee: Toshiba Memory Corporation. Active years: 2017-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Koji Matsuo. Retrieved from https://idiyas.com/inventor/koji-matsuo-7hw011bt

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 66.7

Average Co-Inventor Count = 4.4

ph-index = 1

Forward Citations = 3(Granted Patents)


Location History:

  • Ama Aichi, JP (2018)
  • Ama, JP (2017 - 2019)

Company Filing History:


Years Active: 2017-2019

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3 patents (USPTO):Explore Patents

Title: Innovations by Koji Matsuo

Introduction

Koji Matsuo is a notable inventor based in Ama, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of three patents. His work is primarily associated with Toshiba Memory Corporation, where he has been instrumental in developing advanced semiconductor devices.

Latest Patents

One of Matsuo's latest patents is for a semiconductor device. According to one embodiment, this semiconductor device includes an interconnection layer, a stacked body, a plurality of separation portions, a semiconductor body, a charge storage portion, an n-type semiconductor region, and a p-type semiconductor region. The n-type semiconductor region is strategically placed between the separation portion and the first interconnection part, ensuring contact with both the first interconnection part and the second semiconductor part. Similarly, the p-type semiconductor region is located between the separation portion and the second interconnection part, maintaining contact with the second interconnection part and the second semiconductor part.

Another significant patent is for a pattern forming method. This method involves providing a substrate with a pattern formation region and a peripheral region, where the peripheral region has a surface lower than that of the pattern formation region. The process includes forming an auxiliary pattern with a predetermined height on at least a portion of the peripheral region, applying a resist layer on the pattern formation region, and imprinting the resist layer using a template that covers both the pattern formation region and a portion of the peripheral region.

Career Highlights

Throughout his career, Koji Matsuo has focused on innovations in semiconductor technology. His work at Toshiba Memory Corporation has positioned him as a key player in the development of cutting-edge semiconductor devices. His patents reflect his commitment to advancing technology and improving the efficiency of semiconductor applications.

Collaborations

Matsuo has collaborated with several talented individuals in his field, including Tatsuro Shinozaki and Gaku Sudo. These collaborations have contributed to the successful development of his innovative patents and have fostered a collaborative environment for technological advancement.

Conclusion

Koji Matsuo's contributions to semiconductor technology through his patents and collaborations highlight his role as a significant inventor in the industry. His work continues to influence advancements in semiconductor devices, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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